Static Power Side-Channel Analysis of a Threshold Implementation Prototype Chip
26.12.2016
From abstract—The static power consumption of modern CMOS
devices has become a substantial concern in the context of the
side-channel security of cryptographic hardware. The continuous
growth of the leakage power dissipation in nanometer-scaled
CMOS technologies is not only inconvenient for effective low
power designs, but does also create a new target for power
analysis adversaries. In this paper, we present the first experimental
results of a static power side-channel analysis targeting an
ASIC implementation of a provably first-order secure hardware
masking scheme.